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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003-2005, zarlink semiconductor inc. all rights reserved. features ? central office quality dtmf transmitter/receiver ? low power consumption ? high speed intel micro interface ? adjustable guard time ? automatic tone burst mode ? call progress tone detection to -30 dbm applications ? credit card systems ? paging systems ? repeater systems/mobile radio ? interconnect dialers ? personal computers description the mt8888c is a monolithic dtmf transceiver with call progress filter. it is fabricated in cmos technology offering low power consumption and high reliability. the receiver section is based upon the industry standard mt8870 dtmf receiver while the transmitter utilizes a switched capacitor d/a converter for low distortion, high accuracy dtmf signalling. internal counters provide a burst mode such that tone bursts can be transmitted with prec ise timing. a call progress filter can be selected allowing a microprocessor to analyze call progress tones. the mt8888c utilizes an intel micro interface, which allows the device to be connected to a number of popular microcontro llers with minima l external logic. september 2005 ordering information mt8888ce 20 pin pdip tubes mt8888cs 20 pin soic tubes mt8888cn 24 pin ssop tubes mt8888cp 28 pin plcc tubes mt8888ce1 20 pin pdip* tubes mt8888cs1 20 pin soic* tubes mt8888cn1 24 pin ssop* tubes MT8888CP1 28 pin plcc* tubes mt8888cpr 28 pin plcc tape & reel mt8888csr 20 pin soic tape & reel mt8888csr1 20 pin soic* t ape & reel mt8888cpr1 28 pin plcc* tape & reel *pb free matte tin -40 c to +85 c mt8888c integrated dtmf transceiver with intel micro interface data sheet figure 1 - functional block diagram tone in+ in- gs osc1 osc2 v dd v ref v ss est st/gt d0 d1 d2 d3 irq /cp rd cs wr rs0 d/a converters row and column counters transmit data register data bus buffer tone burst gating cct. + - oscillator circuit bias circuit control logic digital algorithm and code converter control logic steering logic status register control register a control register b receive data register interrupt logic i/o control low group filter high group filter dial tone filter
mt8888c data sheet 2 zarlink semiconductor inc. figure 2 - pin connections pin description pin # name description 20 24 28 11 1 in+ non-inverting op-amp input. 22 2 in- inverting op-amp input. 33 4 gs gain select . gives access to output of front end differential amplifier for connection of feedback resistor. 44 6 v ref reference voltage output (v dd /2). 55 7 v ss ground (0v ). 6 6 8 osc1 dtmf clock/oscillat or input. connect a 4.7 m ? resistor to vss if crystal oscillator is used. 77 9osc2 oscillator output. a 3.579545 mhz crystal connected between osc1 and osc2 completes the internal oscillator circui t. leave open circuit when osc1 is driven externally. 8 10 12 tone output from internal dtmf transmitter. 91113 wr write microprocessor input. ttl compatible. 10 12 14 cs chip select input. active low. this signal must be qualified externally by address latch enable (ale) signal, see figure 14. 11 13 15 rs0 register select input. refer to table 3 for bit interpretation. ttl compatible. 12 14 17 rd read microprocessor input. ttl compatible. 13 15 18 irq /cp interrupt request/call progress (open drain) output. in interrupt mode, this output goes low when a valid dtmf tone burst has been transmitted or received. in call progress mode, this pin will output a rectangular signal r epresentative of the input signal applied at t he input op-amp. the input si gnal must be within the bandwidth limits of the call progress filter, see figure 8. 14-17 18-21 19-22 d0-d3 microprocessor data bus . high impedance when cs = 1 or rd = 1. ttl compatible. 1 2 3 4 5 6 7 8 9 10 11 12 20 19 18 17 16 15 14 13 in+ in- gs vref vss osc1 osc2 tone wr cs vdd st/gt est d3 d2 d1 d0 irq /cp rd rs0 nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 in+ in- gs vref vss osc1 osc2 nc tone wr cs vdd st/gt est d3 d2 d1 d0 nc nc irq /cp rd rs0 24 pin ssop 20 pin plast ic dip/soic 28 pin plcc 4 5 6 7 8 9 10 11 25 24 23 22 21 20 19 ? g s nc nc nc d3 d2 d1 nc vref vss osc1 osc2 nc nc r d 3 2 1 2 8 2 7 2 6 1 2 1 3 1 4 1 5 1 6 1 7 1 8 n c i n - i n + v d d s t / g t e s t t o n e w r c s r s o n c i r q / c p d0
mt8888c data sheet 3 zarlink semiconductor inc. 1.0 functional description the mt8888c integrated dtmf transceiver consists of a hi gh performance dtmf receiver with an internal gain setting amplifier and a dtmf generator which employs a burst counter to synthesize precise tone bursts and pauses. a call progress mode can be selected so that frequencies within the specif ied passband can be detected. the intel micro interface allows microcontrollers, su ch as the 8080, 80c31/51 and 8085, to access the mt8888c internal registers. 2.0 input configuration the input arrangement of the mt8888c provides a differenti al-input operational amplifier as well as a bias source (v ref ), which is used to bias the inputs at v dd /2. provision is made for connection of a feedback resistor to the op- amp output (gs) for gain adjustment. in a single-ended co nfiguration, the input pins are connected as shown in figure 3. figure 4 shows the necessary connec tions for a differential input configuration. 3.0 receiver section separation of the low and high group tones is achieved by applying the dtmf signal to t he inputs of two sixth-order switched capacitor bandpass filters, the bandwidths of which correspond to the low and high group frequencies (see table 1). these filters incorporate notches at 350 hz and 440 hz for excepti onal dial tone rejection. each filter output is followed by a single order switched capacitor f ilter section, which smooths the signals prior to limiting. limiting is performed by high-gain comparators which are provided with hysteresis to prevent detection of unwanted low-level signals. the outputs of the comparators provide full rail logic swings at the frequencies of the incoming dtmf signals. 18 22 26 est early steering output. presents a logic high once the digital algorithm has detected a valid tone pair (signal conditi on). any momentary loss of signal condition will cause est to return to a logic low. 19 23 27 st/gt steering input/guard time output (bidirectional). a voltage greater than v tst detected at st causes the device to regist er the detected tone pair and update the output latch. a voltage less than v tst frees the device to accept a new tone pair. the gt output acts to reset the external steering time-constant; its state is a function of est and the voltage on st. 20 24 28 v dd positive power supply (5 v typical). 8, 9, 16,17 3,5,10, 11,16, 23,25 nc no connection. pin description (continued) pin # name description 20 24 28
mt8888c data sheet 4 zarlink semiconductor inc. figure 3 - single-ended input configuration figure 4 - differential input configuration c r in r f in+ in- gs v ref voltage gain (a v ) = r f / r in mt8888c c1 c2 r1 r2 r3 r4 r5 in+ in- gs v ref mt8888c differential input amplifier c1 = c2 = 10 nf r1 = r4 = r5 = 100 k ? r2 = 60k ? , r3 = 37.5 k ? r3 = (r2r5)/(r2 + r5) voltage gain (a v diff) - r5/r1 input impedance (z in diff) = 2 r1 2 + (1/ c) 2
mt8888c data sheet 5 zarlink semiconductor inc. note: 0= logic low, 1= logic high following the filter section is a decoder employing digita l counting techniques to determine the frequencies of the incoming tones and to verify that they correspond to standard dtmf frequencies. a complex averaging algorithm protects against tone simulation by extraneous signals su ch as voice while providing tolerance to small frequency deviations and variations. this averaging algorithm has been developed to ensure an optimum combination of immunity to talk-off and tolerance to the presence of interfering frequencies (third tones) and noise. when the detector recognizes the presence of two valid tones (this is referred to as the ?signal condition? in some industry specifications) the ?early steering? (est) output will go to an active state. any subs equent loss of signal condition will cause est to assume an inactive state. 4.0 steering circuit before registration of a decoded tone pair, the receiver che cks for a valid signal duration (referred to as character recognition condition). this check is performed by an extern al rc time constant driven by est. a logic high on est causes v c (see figure 5) to rise as the capacitor discharges. pr ovided that the signal condition is maintained (est remains high) for the validation period (t gtp ), v c reaches the threshold (v tst ) of the steering l ogic to register the tone pair, latching its corresponding 4-bit code (see table 1) into the receive data register. at this point the gt output is activated and drives v c to v dd . gt continues to drive high as long as est remains high. finally, after a short delay to allow the output latch to settle, the delaye d steering output flag goes hi gh, signalling that a received tone pair has been registered. the status of the delayed steering flag can be monitored by checking the appropriate bit in the status register. if interrupt mode has been selected, the irq /cp pin will pull low when the delayed steering flag is active. the contents of the output latch are u pdated on an active delayed steering tran sition. this data is presented to the four bit bidirectional data bus when the receive data r egister is read. the steering circuit works in reverse to validate the interdigit pause between signals. thus, as well as rejecting signals too short to be considered valid, the f low f high digit d 3 d 2 d 1 d 0 697 1209 1 0 0 0 1 697 1336 2 0 0 1 0 697 1477 3 0 0 1 1 770 1209 4 0 1 0 0 770 1336 5 0 1 0 1 770 1477 6 0 1 1 0 852 1209 7 0 1 1 1 852 1336 8 1 0 0 0 852 1477 9 1 0 0 1 941 1336 0 1 0 1 0 941 1209 * 1 0 1 1 941 1477 # 1 1 0 0 697 1633 a 1 1 0 1 770 1633 b 1 1 1 0 852 1633 c 1 1 1 1 941 1633 d 0 0 0 0 table 1 - functional encode/decode table
mt8888c data sheet 6 zarlink semiconductor inc. receiver will tolerate signal interrupt ions (drop out) too short to be consider ed a valid pause. this facility, together with the capability of selecting the steering time constant s externally, allows the designer to tailor performance to meet a wide variety of system requirements. figure 5 - basic steering circuit 5.0 guard time adjustment the simple steering circuit shown in figure 5 is adequat e for most applications. component values are chosen according to the following inequalities (see figure 7): t rec t dpmax +t gtpmax - t damin t rec t dpmin +t gtpmin - t damax t id t damax +t gtamax - t dpmin t do t damin +t gtamin - t dpmax v dd v dd st/gt est c1 vc r1 mt8888c t gta = (r1c1) in (v dd / v tst ) t gtp = (r1c1) in [v dd / (v dd -v tst )]
mt8888c data sheet 7 zarlink semiconductor inc. figure 6 - guard time adjustment the value of t dp is a device parameter (see ac el ectrical characteristics) and t rec is the minimum signal duration to be recognized by the receiver. a value for c1 of 0.1 f is recommended for most applications, leaving r1 to be selected by the designer. different steering arrangement s may be used to select independent tone present (t gtp ) and tone absent (t gta ) guard times. this may be necessary to meet system specifications which place both accept and reject limits on tone duration and interdigital pause. guard time adjustment also allows the designer to tailor system parameters such as talk off and noise immunity. increasing t rec improves talk-off performance since it reduces th e probability that tones simulated by speech will maintain a valid signal condition long enough to be registered. alternatively, a relatively short t rec with a long t do would be appropriate for extremely noisy environments where fast acquisition time and immunity to tone drop-outs are required. design information for g uard time adjustment is shown in figur e 6. the receiver timing is shown in figure 7 with a description of the events in figure 9. 6.0 call progress filter a call progress mode, using the mt8888c, can be selected allowing the detection of va rious tones, which identify the progress of a telephone call on the network. th e call progress tone input and dtmf input are common, however, call progress tones can only be detected w hen cp mode has been selected. dtmf signals cannot be detected if cp mode has been selected (see table 7). fi gure 8 indicates the useful detect bandwidth of the call progress filter. frequencies presented to t he input, which are within the ?accept? bandwidth limits of the filter, are hard-limited by a high gain comparator with the irq /cp pin serving as the output. the squarewave output obtained from the schmitt trigger can be analyzed by a microproces sor or counter arrangement to determine the nature of the call progress tone bei ng detected. frequencies which are in the ?reject? area will not be detected and consequently the irq /cp pin will remain low. v dd st/gt est v dd st/gt est c1 r1 r2 c1 r1 r2 t gta = (r1c1) in (v dd /v tst ) t gtp = (r p c1) in [v dd / (v dd -v tst )] r p = (r1r2) / (r1 + r2) t gta = (r p c1) in (v dd /v tst ) t gtp = (r1c1) in [v dd / (v dd -v tst )] r p = (r1r2) / (r1 + r2) a) decreasing tgtp; (tgtp < tgta) b) decreasing tgta; (tgtp > tgta)
mt8888c data sheet 8 zarlink semiconductor inc. figure 7 - receiver timing diagram figure 8 - call progress response v in est st/gt rx 0 -rx 3 b3 b2 read status register irq /cp events abcdef t rec t rec t id t do tone #n tone #n + 1 tone #n + 1 t dp t da t gtp t gta t pstrx t pstb3 decoded tone # (n-1) # n # (n + 1) v tst level (dbm) frequency (hz) -25 0 250 500 750 = reject = may accept = accept
mt8888c data sheet 9 zarlink semiconductor inc. figure 9 - description of timing events 7.0 dtmf generator the dtmf transmitter employed in the mt8888c is cap able of generating all sixteen standard dtmf tone pairs with low distortion and high accuracy. all frequencies ar e derived from an external 3.579545 mhz crystal. the sinusoidal waveforms for the individual tones are digi tally synthesized using row and column programmable dividers and switched capacitor d/a converters. the ro w and column tones are mixe d and filtered providing a dtmf signal with low total harmonic dist ortion and high accuracy. to specify a dtmf signal, data conforming to the encoding format shown in table 1 must be written to the transmit data register. note that this is the same as the receiver output code. the indivi dual tones which are generated (f low and f high ) are referred to as low group and high group tones. as seen from the table, the low group frequencies are 697, 770, 852 and 94 hz. the high group frequencies are 1209, 1336, 1477 and 1633 hz. typically, the high group to low group amplitude ratio (twist) is 2 db to compensate for high group attenuation on long loops. the period of each tone consists of 32 equal time segmen ts. the period of a tone is co ntrolled by varying the length of these time segments. during write o perations to the transmit data register the 4 bit data on the bus is latched and converted to 2 of 8 coding for use by the programmabl e divider circuitry. this co de is used to specify a time segment length, which will ultimately determine the frequency of the tone. wh en the divider reac hes the appropriate count, as determined by the input code, a reset pulse is issued and the counter starts again. the number of time segments is fixed at 32, however, by varying the segment length as described above the frequency can also be varied. the divider output cloc ks another counter, which addresses the sinewave lookup rom. explanation of events a) tone bursts detected, tone duration invalid, rx data register not updated. b) tone #n detected, tone duration valid, to ne decoded and latched in rx data register. c) end of tone #n detected, tone absent duration valid, information in rx data register retained until next valid tone pair. d) tone #n+1 detected, tone duration valid, to ne decoded and latched in rx data register. e) acceptable dropout of tone #n+1, tone absent duration invalid, data remains unchanged. f) end of tone #n+1 detected, tone absent durati on valid, information in rx data register retained until next valid tone pair. explanation of symbols v in dtmf composite input signal. est early steering output. indicates detection of valid tone frequencies. st/gt steering input/guard time output. drives external rc timing circuit. rx 0 -rx 3 4-bit decoded data in receive data register b3 delayed steering. indicates that valid frequencies have been present/absent for the required guard time thus constituting a valid signal. active low for the duration of a valid dtmf signal. b2 indicates that valid data is in the receive data register. the bit is cleared after the status register is read. irq /cp interrupt is active indicating that new data is in the rx data register. the interrupt is cleared after the status register is read. t rec maximum dtmf signal duration not detected as valid. t rec minimum dtmf signal duration required for valid recognition. t id minimum time between valid sequential dtmf signals. t do maximum allowable dropout during valid dtmf signal. t dp time to detect valid frequencies present. t da time to detect valid frequencies absent. t gtp guard time, tone present. t gta guard time, tone absent.
mt8888c data sheet 10 zarlink semiconductor inc. the lookup table contains codes which are used by the sw itched capacitor d/a converter to obtain discrete and highly accurate dc voltage levels. two identical circuits are employed to produce row and column tones, which are then mixed using a low noise summi ng amplifier. the oscillator described ne eds no ?start-up? time as in other dtmf generators since the crystal oscillator is running continuously thus provid ing a high degree of tone burst accuracy. a bandwidth limiting filter is incorporated and se rves to attenuate distortion products above 8 khz. it can be seen from figure 8 that the distor tion products are very low in amplitude. figure 10 - spectrum plot 8.0 burst mode in certain telephony applications it is required that dtmf signals being generated are of a specific duration determined either by the pa rticular application or by any one of the exchange transmit ter specifications currently existing. standard dtmf signal timing can be accomplished by making use of the burst mode. the transmitter is capable of issuing symmetric bursts/pauses of pre determined duration. this burst/pause duration is 51 ms 1ms, which is a standard interval for autodialer and central of fice applications. after the bur st/pause has been issued, the appropriate bit is set in the status register indicating that the transmitter is ready for more data. the timing described above is available when dtmf mode has been selected. however, when cp mode (call progress mode) is selected, the burst/pause duration is doubled to 102 ms 2 ms. note that when cp mode and burst mode have been selected, dtmf tones may be transmitted only and not received. in applications where a non-standard burst/pause time is desirable, a software timing loop or external timer can be used to provide the timing pulses when the burst mode is disabled by ena bling and disabling the transmitter. scaling information 10 db/div start frequency = 0 hz stop frequency = 3400 hz marker frequency = 697 hz and 1209 hz
mt8888c data sheet 11 zarlink semiconductor inc. 9.0 single tone generation a single tone mode is available whereb y individual tones from the low group or high group can be generated. this mode can be used for dtmf test equipment applicat ions, acknowledgment tone generation and distortion measurements. refer to control register b description for details. 10.0 distortion calculations the mt8888c is capable of producing precise tone bursts with minimal er ror in frequency (see table 2). the internal summing amplifier is followed by a first-order lowpass switched capacitor filter to minimize harmonic components and intermodulation products. the total harmonic distortion for a single tone can be calculated using equation 1, which is the ratio of the total power of all the extraneous frequencies to the power of the fundamental frequency expressed as a percentage. figure 11 - equation 1. thd (%) for a single tone the fourier components of the tone output correspond to v 2f .... v nf as measured on the output waveform. the total harmonic distortion for a dual tone can be calculated using equation 2. v l and v h correspond to the low group amplitude and high group amplitude, respectively and v 2 imd is the sum of all the inte rmodulation components. the internal switched-capacitor filter following the d/a conver ter keeps distortion products down to a very low level as shown in figure 10. figure 12 - equation 2. thd (%) for a dual tone active input output frequency (hz) %error specified actual l1 697 699.1 +0.30 l2 770 766.2 -0.49 l3 852 847.4 -0.54 l4 941 948.0 +0.74 h1 1209 1215.9 +0.57 h2 1336 1331.7 -0.32 h3 1477 1471.9 -0.35 h4 1633 1645.0 +0.73 table 2 - actual frequencies versus standard requirements thd (%) = 100 v fundamental v 2 2f + v 2 3f + v 2 4f + .... v 2 nf v 2 l + v 2 h v 2 2l + v 2 3l + .... v 2 nl + v 2 2h + v 2 3h + .. v 2 nh + v 2 imd thd (%) = 100
mt8888c data sheet 12 zarlink semiconductor inc. 11.0 dtmf clock circuit the internal clock circuit is complet ed with the addition of a standard televi sion color burst crystal. the crystal specification is as follows: frequency: 3.579545 mhz frequency tolerance: 0.1% resonance mode: parallel load capacitance: 18pf maximum series resistance: 150 ohms maximum drive level: 2mw e.g. cts knights mp036s toyocom tqc-203-a-9s a number of mt8888c devices can be connected as shown in figure 13 such that only one crystal is required. alternatively, the osc1 inputs on all devices can be driven from a ttl buffer with the osc2 outputs left unconnected. figure 13 - common crystal connection 12.0 microprocessor interface the mt8888c incorporates an intel micropr ocessor interface which is compatible with fast versions (16 mhz) of the 80c51. no wait cycles need to be inserted. figure 19 and figure 20 are the timing diagrams for the intel 8031, 8051 an d 8085 (5 mhz) microcontrollers. by nanding the address latch enable (ale) output with the high-byte address (p2) decode output, cs is generated. figure 14 summarizes the connection of these intel processors to the mt8888c transceiver. the microprocessor interface provides access to five internal registers. the read-only receive data register contains the decoded output of the last valid dtmf digit received. data entered into the write-only transmit data register will determine which tone pair is to be generat ed (see table 1 for coding details). transceiver control is accomplished with two control registers (see table 6 and table 7), cra and crb, which have the same address. a write operation to crb is executed by first setting the mo st significant bit (b3) in cra. the following write operation to the same address will then be di rected to crb, and subsequent write cyc les will be directed back to cra. the read-only status register indicates the current transceiver state (see table 8). a software reset must be included at the beginning of a ll programs to initialize the control registers upon power-up or power reset (see figure 19). refer to tables 4- 7 for bit descriptions of the two control registers. the multiplexed irq /cp pin can be programmed to generate an interrupt upon validation of dtmf signals or when the transmitter is ready for more data (burst mode only). alternatively, this pin can be configured to provide a squarewave output of the ca ll progress signal. the irq /cp pin is an open drain out put and requires an external pull-up resistor (see figure 15). mt8888c osc1 osc2 mt8888c osc1 osc2 mt8888c osc1 osc2 3.579545 mhz
mt8888c data sheet 13 zarlink semiconductor inc. rs0 wr rd function 0 0 1 write to transmit data register 0 1 0 read from receive data register 1 0 1 write to control register 1 1 0 read from status register table 3 - internal register functions b3 b2 b1 b0 rsel irq cp/dtmf tout table 4 - cra bit positions b3 b2 b1 b0 c/r s/d test burst enable table 5 - crb bit positions bit name description b0 tout tone output control. a logic high enables the tone output; a logic low turns the tone output off. this bit controls all transmit tone functions. b1 cp/dtmf call progress or dtmf mode select. a logi c high enables the receiv e call progress mode; a logic low enables dtmf mode. in dtmf mode the device is capable of receiving and transmitting dtmf signals. in cp mode a re ctangular wave representation of the received tone signal will be present on the irq /cp output pin if irq has been enabled (control register a, b2=1). in order to be detected, cp signals must be within the bandwidth specified in the ac electrical characteristics for call progress. note: dtmf signals cannot be detected when cp mode is selected. b2 irq interrupt enable. a logic high enables the interrupt functi on; a logic low deactivates the interrupt function. when irq is enabled and dt mf mode is selected (control register a, b1=0), the irq /cp output pin will go low when either 1) a valid dtmf signal has been received for a valid guard time duration, or 2) the transmitter is ready for more data (burst mode only). b3 rsel register select. a logic high selects control register b for the next wr ite cycle to the control register address. after writing to control register b, the following control register write cycle will be directed to control register a. table 6 - control register a description
mt8888c data sheet 14 zarlink semiconductor inc. bit name description b0 burst burst mode select. a logic high deactivates burst mode; a logic low enables burst mode. when activated, the digital co de representing a dtmf signal (see table 1) can be written to the transmit regist er, which will result in a transmit dtmf tone burst an d pause of equal durations (typically 51 msec). following the paus e, the status register will be updated (b1 - transmit data register empt y), and an interrupt will occur if the interrupt mode has been enabled. when cp mode (control register a, b1) is enabled the normal tone burst and pause durations are extended from a typica l duration of 51 msec to 102 msec. when burst is high (deactivated) the transmit tone burst duration is determined by the tout bit (control register a, b0). b1 test test mode control. a logic high enables the test mode; a logic low deactivates the test mode. when test is enabled and dtmf mode is selected (control regi ster a, b1=0), the signal present on the irq /cp pin will be analogous to the state of the delayed steering bit of the status regi ster (see figure 7, signal b3). b2 s/d single or dual tone generation. a logic high selects the single tone output; a logic low selects the dual tone (dtmf) output. the single tone generation function requires further selection of either the row or column to nes (low or high group) through the c/r bit (control register b, b3). b3 c/r column or row tone select. a logic high selects a column tone output; a logic low selects a row tone output. this function is used in conjunction with the s/d bit (control register b, b2). table 7 - control register b description bit name status flag set status flag cleared b0 irq interrupt has occurred. bit one (b1) or bit two (b2) is set. interrupt is inactive. cleared after status register is read. b1 transmit data register empty (burst mode only) pause duration has terminated and transmitter is ready for new data. cleared after status register is read or when in non-burst mode. b2 receive data register full valid data is in the receive data register. cleared after status register is read. b3 delayed steering set upon the valid detection of the absence of a dtmf signal. cleared upon the detection of a valid dtmf signal. table 8 - status register description
mt8888c data sheet 15 zarlink semiconductor inc. figure 14 - mt8888c interface connections for various intel micros figure 15 - application circuit (single-ended input) 8031/8051 8080/8085 mt8888c a8-a15 po rd wr cs rd wr rs0 d0-d3 a8 * microprocessor based systems can inject undesirable noise into the supply rails. the performance of the mt8888c can be optimized by keeping noise on the supply rails to a minimum. the decoupling capacitor (c3) should be connected close to the device and ground loops should be avoided. in+ in- gs vref vss osc1 osc2 tone wr cs vdd st/gt est d3 d2 d1 d0 irq /cp rd rs0 dtmf/cp input dtmf output c1 r1 r2 x-tal c4 r l v dd c3 c2 r4 r3 to p or c mt8880c r5 notes: r1, r2 = 100 k ? 1% r3 = 374 k ? 1% r4 = 3.3 k ? 10% r l = 10 k ? (min.) c1 = 100 nf 5% c2 = 100 nf 5% c3 = 100 nf 10%* c4 = 10 nf 10% x-tal = 3.579545 mhz r5 = 4.7 m ? 10%
mt8888c data sheet 16 zarlink semiconductor inc. figure 16 - test circuits figure 17 - application notes test point mmd6150 (or equivalent) 5.0 vdc 2.4 k ? 24 k ? 130 pf mmd7000 (or equivalent) test point 5.0 vdc 3 k ? 100 pf test load for irq /cp pin test load for d0-d3 pins initialization procedure a software reset must be included at the beginning of all programs to initialize the control registers after power up.the initialization procedure should be implemented 100ms after power up. description: control data rs0 wr rd b3 b2 b1 b0 1) read status register 1 1 0 x x x x 2) write to control register 1 0 1 0 0 0 0 3) write to control register 1 0 1 0 0 0 0 4) write to control register 1 0 1 1 0 0 0 5) write to control register 1 0 1 0 0 0 0 6) read status register 1 1 0 x x x x typical control sequence for burst mode applications transmit dtmf tones of 50 ms burst/50 ms pause and receive dtmf tones. sequence: rs0 wr rd b3 b2 b1 b0 1) write to control register a 1 0 1 1 1 0 1 (tone out, dtmf, irq , select control register b) 2) write to control register b 1 0 1 0 0 0 0 (burst mode) 3) write to transmit data register 0 0 1 0 1 1 1 (send a digit 7) 4) wait for an interrupt or poll status register 5) read the status register 1 1 0 x x x x -if bit 1 is set, the tx is ready for the next tone, in which case... write to transmit register 0 0 1 0 1 0 1 (send a digit 5) -if bit 2 is set, a dtmf tone has been received, in which case.... read the receive data register 0 1 0 x x x x -if both bits are set... read the receive data register 0 1 0 x x x x write to transmit data register 0 0 1 0 1 0 1 note: in the tx burst mode, status register bit 1 will not be set until 100 ms ( 2 ms) after th e data is written to the tx data register. in extended burst mode this time will be doubled t o 200 ms ( 4 ms) .
mt8888c data sheet 17 zarlink semiconductor inc. * exceeding these values may cause permanent damage. functional operation under these conditions is not implied. ? typical figures are at 25 c and for design aid only: not guaranteed and not subject to production testing. absolute maximum ratings * parameter symbol min. max. units 1 power supply voltage v dd -v ss v dd 6v 2 voltage on any pin v i v ss -0.3 v dd +0.3 v 3 current at any pin (except v dd and v ss )10ma 4 storage temperature t st -65 +150 c 5 package power dissipation p d 1000 mw recommended operating conditions - voltages are with respect to ground (v ss ) unless otherwise stated. parameter sym. min. typ. ? max. units test conditions 1 positive power supply v dd 4.75 5.00 5.25 v 2 operating temperature t o -40 +85 c 3 crystal clock frequency f clk 3.575965 3.579545 3.583124 mhz dc electrical ch aracteristics - ? - v ss =0 v. characteristics sym. min. typ. ? max. units test conditions 1 s u p operating supply voltage v dd 4.75 5.0 5.25 v 2 operating supply current i dd 7.0 11 ma 3 power consumption p c 57.8 mw 4 i n p u t s high level input voltage (osc1) v iho 3.5 v note 9* 5 low level input voltage (osc1) v ilo 1.5 v note 9* 6 steering threshold voltage v tst 2.2 2.3 2.5 v v dd =5v 7 o u t p u t s low level output voltage (osc2) v olo 0.1 v no load note 9* 8 high level output voltage (osc2) v oho 4.9 v no load note 9* 9 output leakage current (irq) i oz 110 av oh =2.4 v 10 v ref output voltage v ref 2.4 2.5 2.6 v no load, v dd =5v 11 v ref output resistance r or 1.3 k ? 12 d i g i t a l low level input voltage v il 0.8 v 13 high level input voltage v ih 2.0 v 14 input leakage current i iz 10 av in =v ss to v dd 15 data bus source current i oh -1.4 -6.6 ma v oh =2.4v 16 sink current i ol 2.0 4.0 ma v ol =0.4v
mt8888c data sheet 18 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd =5v and for design aid only: not guaranteed and not subject to production testing. * see ?notes? following ac electrical characteristics tables. figures are for design aid only: not guaranteed and not subject to production testing. characteristics are over recommended operating conditions unless otherwise stated. ? characteristics are over recommended operating conditions (unless otherwise stated) using the test circuit shown in figure 15. 17 est and st/gt source current i oh -0.5 -3.0 ma v oh =4.6v 18 sink current i ol 24 mav ol =0.4v 19 irq / cp sink current i ol 416 mav ol =0.4v electrical character istics gain setting amplifier - voltages are with respect to ground (vss) unless otherwise stated, vss= 0v. characteristics sym. min. typ. max. units test conditions 1 input leakage current i in 100 na v ss v in v dd 2 input resistance r in 10 m ? 3 input offset voltage v os 25 mv 4 power supply rejection psrr 50 db 1 khz 5 common mode rejection cmrr 40 db 6 dc open loop voltage gain a vol 40 db c l = 20p 7 unity gain bandwidth bw 1.0 mhz c l = 20p 8 output voltage swing v o 0.5 v dd -0.5 v r l 100 k ? to v ss 9 allowable capacitive load (gs) c l 100 pf pm>40 10 allowable resistive load (gs) r l 50 k ? v o = 4vpp 11 common mode range v cm 1.0 v dd -1.0 v r l = 50k ? mt8888c ac electrical characteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. characteristics sym. min. typ. ? max. units notes* 1 r x valid input signal levels (each tone of composite signal) -29 +1 dbm 1,2,3,5,6 27.5 869 mv rms 1,2,3,5,6 dc electrical character istics (continued) - ? - v ss =0 v. (continued) characteristics sym. min. typ. ? max. units test conditions
mt8888c data sheet 19 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated. ? typical figures are at 25 c, v dd = 5 v, and for design aid only: not guaranteed and not subject to production testing. * *see ?notes? following ac electrical characteristics tables. ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd =5 v, and for design aid only: not guaranteed and not subject to production testing ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd =5 v, and for design aid only: not guaranteed and not subject to production testing ac electrical ch aracteristics ? - voltages are with respect to ground (v ss ) unless otherwise stated. f c =3.579545 mhz characteristics sym. min. typ. ? max. units notes* 1 r x positive twist accept 8 db 2,3,6,9 2 negative twist accept 8 db 2,3,6,9 3 freq. deviation accept 1.5% 2hz 2,3,5 4 freq. deviation reject 3.5% 2,3,5 5 third tone tolerance -16 db 2,3,4,5,9,10 6 noise tolerance -12 db 2,3,4,5,7,9,10 7 dial tone tolerance 22 db 2,3,4,5,8,9 ac electrical ch aracteristics ? - call progress - voltages are with respect to ground (v ss ), unless otherwise stated. characteristics sym. min. typ. ? max. units conditions 1 accept bandwidth f a 310 500 hz @ -25 dbm, note 9 2 lower freq. (reject) f lr 290 hz @ -25 dbm 3 upper freq. (reject) f hr 540 hz @ -25 dbm 4 call progress tone detect level (total power) -30 dbm ac electrical ch aracteristics ? - dtmf reception - typical dtmf tone accept and reject requirements. actual values are user selectable as per figures 5, 6 and 7. characteristics sym. min. typ. ? max. units conditions 1 minimum tone accept duration t rec 40 ms 2 maximum tone reject duration t rec 20 ms 3 minimum interdigit pause duration t id 40 ms 4 maximum tone drop-out duration t do 20 ms
mt8888c data sheet 20 zarlink semiconductor inc. ? timing is over recommended temperature & power supply voltages. ? typical figures are at 25 c and for design aid only: not guaranteed and not subject to production testing. ac electrical ch aracteristics ? - voltages are with respect to ground (v ss ), unless otherwise stated. characteristics sym. min. typ. ? max. units conditions 1 t o n e i n tone present detect time t dp 3 11 14 ms note 11 2 tone absent detect time t da 0.5 4 8.5 ms note 11 3 delay st to b3 t pstb3 13 s see figure 7 4 delay st to rx 0 -rx 3 t pstrx 8 s see figure 7 5 t o n e o u t tone burst duration t bst 50 52 ms dtmf mode 6 tone pause duration t ps 50 52 ms dtmf mode 7 tone burst duration (extended) t bste 100 104 ms call progress mode 8 tone pause duration (extended) t pse 100 104 ms call progress mode 9 high group output level v hout -6.1 -2.1 dbm r l =10k ? 10 low group output level v lout -8.1 -4.1 dbm r l =10k ? 11 pre-emphasis db p 023dbr l =10k ? 12 output distortion (singl e tone) thd -35 db 25 khz bandwidth 13 r l =10k ? 14 frequency deviation f d 0.7 1.5 % f c =3.579545 mhz 15 output load resistance r lt 10 50 k ? 16 x t a l crystal/clock frequency f c 3.5759 3.5795 3.5831 mhz 17 clock input rise and fall time t clrf 110 ns ext. clock 18 clock input duty cycle dc cl 40 50 60 % ext. clock 19 capacitive load (osc2) c lo 30 pf ac electrical ch aracteristics ? - mpu interface - voltages are with respect to ground (v ss ), unless otherwise stated. characteristics sym. min. typ. ? max. units conditions 1rd /wr clock frequency f cyc 4.0 mhz figure 18 2rd /wr cycle period t cyc 250 ns figure 18 3rd /wr rise and fall time t r, t f 20 ns figure 18 4 address setup time t as 23 ns figures 19 & 20 5 address hold time t ah 26 ns figures 19 & 20 6 data hold time (read) t dhr 22 ns figures 19 & 20 7rd to valid data delay (read) t ddr 100 ns figures 19 & 20 8rd , wr pulse width low t pwl 150 ns figures 18, 19 & 20 9rd , wr pulse width high t pwh 100 ns figures 18, 19 & 20 10 data setup time (write) t dsw 45 ns figures 19 & 20 11 data hold time (write) t dhw 10 ns figures 19 & 20 12 input capacitance (data bus) c in 5pf
mt8888c data sheet 21 zarlink semiconductor inc. ? characteristics are over recommended operating conditions unless otherwise stated ? typical figures are at 25 c, v dd =5 v, and for design aid only: not guaranteed and not subject to production testing notes: 1. dbm=decibels above or below a reference power of 1 mw into a 600 ohm load. 2. digit sequence consists of all 16 dtmf tones. 3. tone duration=40 ms. tone pause=40 ms. 4. nominal dtmf frequencies are used. 5. both tones in the composite signal have an equal amplitude. 6. the tone pair is deviated by 1.5% 2 hz. 7. bandwidth limited (3 khz) gaussian noise. 8. the precise dial tone frequencies are 350 and 440 hz ( 2%). 9. guaranteed by design and characterization. not subject to production testing. 10. referenced to the lowest amplitude tone in the dtmf signal. 11. for guard time calculation purposes. figure 18 - rd /wr clock pulse figure 19 - 8031/8051/8085 read timing diagram figure 20 - 8031/8051/8085 write timing diagram 13 output capacitance (irq /cp) c out 5pf ac electrical ch aracteristics ? - mpu interface (continued)- voltages are with respect to ground (v ss ), unless otherwise characteristics sym. min. typ. ? max. units conditions t cyc t r t pwh t pwl rd /wr t f rd cs , rs0 data bus t pwl t as t ah t pwh t ddr t dhr wr cs , rs0 data bus t pwl t as t ah t pwh t dsw t dhw

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